To package an integrated circuit (IC) chip, such as a processing device or a memory device, the IC die is typically mounted on a substrate, this substrate often referred to as the “package substrate.” The package substrate may comprise multiple layers—e.g., a base or “core” layer constructed from an insulating material having one or more layers of a dielectric material disposed thereon—and each layer may include circuitry. The circuitry on a given layer may include a number of conductive traces or other conductive elements arranged in a desired pattern. This circuitry on the package substrate is electrically coupled with the leads of a die mounted thereon. For a flip-chip package—employing, for example, Controlled Collapse Chip Connection (or “C4”) assembly techniques—an array of bond pads on the die are coupled to a corresponding array of leads, or “lands”, on the package substrate by an array of connection elements (e.g., solder balls, columns, etc.). Alternatively, the die bond pads may be connected to leads on the package substrate using wire bonding or another suitable process.
The circuitry provided by the package substrate routes the IC chip leads to locations on the package substrate where electrical connections can be established with a next-level component (e.g., a motherboard, a computer system, a circuit board, another IC device, etc.). For example, the substrate circuitry may route all signal lines to a ball-grid array—or, alternatively, a pin-grid array—formed on a lower surface of the package substrate. The ball- or pin-grid array then electrically couples the packaged IC die to the next-level component, which includes a mating array of terminals (e.g., lands, pin sockets, etc.). Alternatively, the circuitry may route the signal lines to locations proximate the periphery of the package substrate, wherein wirebonding may be used to couple the packaged IC chip to the next-level component.
The circuitry formed on the package substrate comprises a number of electrically conductive elements (e.g., traces, leads, lands, vias, etc.) arranged in a desired pattern. A conductive element, such as a trace, typically comprises a trench or other depression formed in a dielectric material that has been filled with an electrically conductive material (e.g., copper or a copper alloy). For multi-layer substrates, a trace on one layer may be electrically coupled to another trace on an adjacent layer (e.g., an underlying or an overlying layer), such as may be accomplished by a conductive via or other suitable structure. The circuitry on any single layer may include tens or even hundreds of individual closely spaced traces and other conductive elements, each trace having a width (and depth) on the order of 30 microns (μm) or less. Distances separating the traces and other conductive elements may also be on the order of several microns (e.g., 10 to 50 μm).
With feature sizes of 30 μm or less, and with electronics manufacturers continually striving to increase circuit density and decrease feature sizes, fabricating package substrates and circuitry for IC device packaging presents numerous design and manufacturing challenges. Typically, to create a desired circuit pattern on the surface of a substrate (or a layer thereof), a series of trenches or other depressions are imprinted on the surface, the trenches corresponding to the desired circuit pattern. The trenches are then filled with a conductive material to create the circuitry. Because of the small feature sizes and separation distances exhibited by the circuit pattern, as noted above, imprinting or otherwise forming the trench pattern in a surface of the substrate (or a layer thereof) is one of the most challenging facets of substrate fabrication.
A number of methods and/or systems have been used to create the trench pattern (or patterns) on a package substrate, including compression molding, cold forming, injection molding, casting, and photolithography. Compression molding uses high pressure and elevated heat to imprint a trench pattern into a surface. However, due to thermal expansion of the tooling under high temperature, compression molding may not be suitable for circuit patterns exhibiting small features sizes and/or separation distances. Cold forming (or “coining”) utilizes high pressure at room temperature to imprint the desired pattern of trenches in a surface. The high pressure present during this process—as well as in compression molding—can, however, lead to a number of problems, including substrate damage (e.g., damage to a previously formed layer in a multi-layer structure) and damage to the tooling. Injection molding, which may not suffer from the potential ill effects of high temperature and/or pressure, is generally suitable for larger substrates, but is less suitable for small substrates having relatively smaller feature sizes. Casting is often too slow for production level manufacturing due to long cure times, and photolithography may not achieve sufficient resolution.
On another front, ultrasonic welding of plastics, as well as metals, is well known. In a typical ultrasonic welding application, two parts (e.g., plastic parts) are joined together by imparting high frequency (e.g., 15 kHz to 40 kHz) mechanical vibrations to the parts at a location of the desired joint. This mechanical energy is transmitted to the parts at the joint area, where this energy is converted to heat through friction. This heat melts the material of each part in a region surrounding the joint, and when vibration is halted, the melted material solidifies to join the two parts.